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rev 1.0 7/5/00 characteristics subject to change without notice. 1 of 15 www.icmic.com block diagram 496 byte eeprom array logic scl sda rst interface data transfer array access enable iso reset response register password array and password verification logic retry counter erase logic 4k x76f400 512 x 8 bit secure serialflash features ?64 - bit password security ?one array (496 bytes) two passwords (16 bytes) ? read password ?write password ?programmable passwords ?retry counter register ? allows 8 tries before clearing of the array ?32-bit response to reset (rst input) ?8 byte sector write mode ?1mhz clock rate ?2-wire serial interface ?low power cmos ?2.5 to 5.5v operation ?standby current less than 1a ?active current less than 3 ma ?high re liability endurance: ?100,000 write cycles ?data retention: 100 years ?available in: ? 8 - lead, soic,tssop description the x76f400 is a password access security superviso r, containing one 3968-bit secure serial flash array. access to the memory array can be controlled by two 64- bit passwords. these passwords protect read and write operations of the memory array. the x76f400 features a serial interface and softwar e protocol allowing operation on a popular 2-wi re bus. the bus signals are a clock input (scl) and a bi-di rectional data input and output (sda). the x76f400 also features a synchronous respo nse to reset, providing an automatic output of a hard-wire d 32-bit data stream, thereby meeting the industry st an dard for memory cards. the x76f400 utilizes xicor?s proprietary direct wri te ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. this x76f400 device has been acquired by ic microsystems from xicor, inc. ic mic ic microsystems tm
x76f400 characteristics subject to change without notice. 2 of 15 rev 1.0 7/5/00 www.icmic.com pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is an open drain serial data input/output pin. dur ing a read cycle, data is shifted out on this pin. during a write cycle, data is shifted in on this pin. in a ll other cases, this pin is in a high impedance state. reset (rst) rst is a device reset pin. when rst is pulsed high, the x76f400 will output 32 bits of fixed data, which conforms to the standard for ?synchronous resp onse- to-reset.? the part must not be in a write cycle fo r the response-to-reset to occur. see figure 7. if power is interrupted during the response-to-reset, the respo nse- to-reset will be aborted and the part will return t o the standby state. the response to reset is ?mas k programmable? only! device operation the x76f400 memory array consists of 62 8-byte sect ors. read or write access to the array always begins at the first address of the sector. read operations th en can continue indefinitely. write operations must total 8 bytes. there are two primary modes of operation for the x76f400; protected read and protected write. pro- tected operations must be performed with one of two 8- byte passwords. the basic method of communication for the de vice is generating a start condition, then transmittin g a com- mand, followed by the correct password. all parts w ill be shipped from the factory with all passwords equal t o ?0.? the user must perform ack polling to determi ne the validity of the password, prior to starting a data transfer (see acknowledge polling). only after the correct p ass word is accepted, and an ack polling has b een performed, can the data transfer occur. see figure 1. to ensure the correct communication, rst must remain low under all conditions except when running a ?response-to-reset sequence?. data is transferred in 8-bit segments, with each tr ansfer being followed by an ack, generated by the receivin g device. if the x76f400 is in a nonvolatile write cy cle a ?no ack? (sda = high) response will be issued in response to loading of the command byte. if a stop is issued prior to the nonvolatile write cycle, the wr ite operation will be terminat ed; the part will then reset and enter into a standby mode. (the basic sequence is illustrated in figure 1.) pin names pin configuration after each transaction is completed, the x76f400 wi ll reset and enter into a standby mode. this will also be the response if an unsuccessful attempt is m ade to access a protected array. symbol description sda serial data input/output scl serial clock input rst reset input v cc supply voltage v ss ground nc no connect sda v cc rst scl nc 1 2 3 4 7 8 6 5 soic v ss nc nc v ss rst sda nc nc 1 2 3 4 7 8 6 5 v cc scl nc tssop
x76f400 characteristics subject to change without notice. 3 of 15 rev 1.0 7/5/00 www.icmic.com figure 1. x76f400 device operation retry counter the x76f400 contains a retry counter. th e retry counter allows 8 accesses with an invalid pa ssword before any action is taken. the counter will increm ent with any combination of incorrect passwords. if th e retry counter overflows, the memory area and both o f the passwords are cleared to ?0.? if a correct password is received prior to retry counter overflow, the retry counter is reset and access is granted. device protocol the x76f400 supports a bi-directional bus ori ented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. the device controlling the tr ansfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive ope ra tions. therefore, the x76f400 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda changes during scl high are reserved for indicating start and stop conditions. refer to figures 2 and 3. start condition all commands are prec eded by the start condition, which is a high to low transition of sda when scl is high. the x76f400 co ntinuously monitors the sda and scl lines for the start condition, and will not respond to any command until this condition is met. a start may be issued t o terminate the input of a control byte or the input data to be written. this will res et the device and leave it ready to begin a new read o r write command. because of the push/pull output, a start cannot be generated while the part is outputt ing data. starts are inhibited while a write is in progress. stop condition all communications must be terminated by a stop con- dition. the stop condition is a low to high transit ion of sda when scl is high. the stop condition is also used to reset the device during a command or dat a input sequence, leaving the device in the st andby power mode. as with starts, stops are inhibited whe n outputting data and while a write is in progress. acknowledge acknowledge is a software convention used to indica te successful data transfer. the transmitting device, either master or slave, will rele ase the bus after transmitting 8 bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received th e 8 bits of data. the x76f400 will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write condition have been selected, the x76f400 will respond with an a cknowl- edge after the receipt of each subsequent 8-bit wor d. load command/address byte load 8-byte password verify password acceptance by use of ack polling read/write data bytes figure 2. data validity scl sda data stable data change
x76f400 characteristics subject to change without notice. 4 of 15 rev 1.0 7/5/00 www.icmic.com figure 3. definition of start and st op conditions table 1. x76f400 instruction set command after start command description password used 1 s 5 s 4 s 3 s 2 s 1 s 0 0 sector write write 1 s 5 s 4 s 3 s 2 s 1 s 0 1 sector read read 1 1 1 1 1 1 0 0 change write password write 1 1 1 1 1 1 1 0 change read password write 0 1 0 1 0 1 0 1 password ack command none scl sda start condition stop condition illegal command codes will be disregarded. the part will respond with a ?no-ack? to the illegal byte and then return to the standby mode. all write/read o pera tions require a password. program operations sector write the sector write mode requires issuing the 8-bit wr ite command followed by the password and then the data bytes transferred as illustrated in figure 4. the write command byte contains the address of the sector to be written. data is written starting at the first addr ess of a sector and 8 bytes must be transferred. after the l ast byte to be transferred is acknowledged, a stop cond i tion is issued which starts the nonvolatile write cycle. if more or less than 8 bytes are transferred, the data in the sector remains unchanged. ack polling once a stop condition is issued to indicate the end of the host?s write sequence, the x76f400 initiates the internal nonvolatile write cycle. in order to take advan tage of the typical 5ms write cycle, ack polling can begin immediately. this involves issuing the start con dition followed by the new command code of 8 bits (first byte of the protocol). if the x76f400 is sti ll busy with the nonvolatile write operation, it will issue a ?no - ack? in response. if the nonvolatile write operatio n is completed, an ?ack? will be returned and the host c an then proceed with the rest of the protocol. data ack polling sequence ack returned? issue new command code write sequence completed enter ack polling issue start no yes proceed
x76f400 characteristics subject to change without notice. 5 of 15 rev 1.0 7/5/00 www.icmic.com after the password sequence, there is always a nonv ola- tile write cycle. this is done to discourage rand om guesses of the password if the device is being tamp ered with. in order to continue the transaction, the x76f400 requires the master to perform a password ack polli ng sequence with the specific command code of 5 5h. as with regular acknowledge polling the user can either time out for 10ms and then issue the ack polling once, or continuously loop as described in the flow. if the password inserted is corre ct, the nonvolatile cycle in response to the password ack polling sequence is over, and an ?ack? is returned. if the password inserted is incorrect, a ?no ack? is returned, even if the nonvolatile cycle is o ver. there- fore, the user cannot be certain that the p assword is incorrect until the 10ms write cycle time has elaps ed. password ack polling sequence read operations read operations are initiated in the same manner as write operations but with a different command code. sector read with sector read, a sector address is supplied with the read command. once the password has been acknowledged data may be read from the secto r. an acknowledge must follow each 8-bit data trans fer. a read operation always begins at the first by te in the sector, but may stop at any time. random accesses t o the array are not possible. continuous reading from the array will return data from successive sector s. after reading the last sector in the array, the address i s auto- matically set to the first sector in the array and data can continue to be read out. after the last bit has been read, a stop condition is generated without sending a preceding acknowledge. ack returned? issue password ack command password load completed enter ack polling issue start no yes proceed
x76f400 characteristics subject to change without notice. 6 of 15 rev 1.0 7/5/00 www.icmic.com figure 4. sector write sequence (password required) figure 5. acknowledge polling figure 6. sector read sequence (password required) p write write password 7 write password 0 s sda wait t wc or ack password command password ack s command if ack, then password matches command host commands host commands x76f400 response x76f400 response wait t wc data ack polling 8 th clk of 8 th pwd. byte ?ack? clk 8 th clk ?ack? clk ?ack? start condition 8 th bit ack or no ack scl sda data n p read read password 7 read password 0 data 0 s sda wait t wc or ack password command password ack s command if ack, then password matches command host commands host commands x76f400 response x76f400 response ack start ack ack ack ack ack start ac k no - ack stop ack ack ack ack start ack ack ack ack ack start ack no - ack stop
x76f400 characteristics subject to change without notice. 7 of 15 rev 1.0 7/5/00 www.icmic.com passwords passwords are changed by sending the ?change read password? or ?change write password? commands in a normal sector write operation. a full 8 bytes conta ining the new password must be sent, following successful transmission of the current write password and a va lid password ack response. the user can use a repeated ack polling command to check that a new password has been written correctly. an ack indicates that the new password is valid. there is no way to read any of the passwords. response - to - reset (default = 1 9 40 aa 55) the iso response-to- reset is controlled by the rst and clk pins. when rst is pulsed high during a clock pulse, the device will output 32 bits of data, one bit per clock, and it resets to the standby state. this con forms to the iso sta ndard for ?synchronous response to reset.? the part must not be in a write cycle for the response-to-reset to occur. after initiating a nonvolatile write cycle, t he rst pin must not be pulsed until the nonvolatile write cycle is complete. if not, the iso response will not be acti vated. if the rst is pulsed high and the clk is within the rst pulse (meet the t nol spec.) in the middle of an iso transaction, it will output the 32 bit sequence again (starting at bit 0). otherwise, this aborts the iso operation and the part returns to standby state. if the rst is pulsed high and the clk is outside the rst pulse (in the middle of an iso transaction), this a borts the iso operation and the part returns to standb y state. if power is interrupted during the response-t o- reset, the response-to-reset will be aborted and the part will return to the standby state. a response-to-reset is not available during a nonvolatile write cycle. figure 7. response to reset (rst) sck so rst byte 0 msb lsb lsb msb 1 lsb msb lsb msb 2 3 10 0 00 11 1 0 0 1 0000 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0
x76f400 characteristics subject to change without notice. 8 of 15 rev 1.0 7/5/00 www.icmic.com absolute maximum ratings temperature under bias .................... ?65c t o +135c storage temperature ........................ ?65c to +150c voltage on any pin with respect to v ss ......................................... ?1v to +7 v d.c. output current ............................... ................ 5ma lead temperature (soldering, 10 seconds) ......... 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional ope ration of the device (at these or any other conditions abo ve those listed in the operational sections of this specific ation) is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0c +70c industrial ?40c +85c supply voltage limits x76f400 4.5v to 5.5v x76f400 ? 2.5 2.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless o therwise specified.) ca pacitance t a = +25c, f = 1mhz, v cc = 5v notes: (1)must perform a stop command after a read command prior to measurement (2)v il min. and v ih max. are for reference only and are not tested (3)this parameter is periodically sampled and not 10 0% test sy mbol parameter limits unit test conditions min. max. i cc1 v cc supply current (read) 1 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i cc2 (3) v cc supply current (write) 3 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i sb1 (1) v cc supply current (standby) 1 a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400 khz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1 a v sda = v scc = v cc other = gnd or v cc ?0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v il (2) input low voltage ?0.5 v cc x 0.1 v v ih (2) input high voltage v cc x 0.9 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol test max. unit conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (rst, scl) 6 pf v in = 0v
x76f400 characteristics subject to change without notice. 9 of 15 rev 1.0 7/5/00 www.icmic.com equivalent a.c. load circuit a.c. test conditions 3v 1.3k output 100pf 5v 1.53k output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf ac characteristics (t a = -40 c to +85 c, v cc = +2.5v to +5.5v, unless otherwise specified) notes: (1)c b = total capacitance of one bus line in pf (2)t aa = 1.1s max below v cc = 2.5v. reset ac specifications power up timing notes: (1)delays are measured from the time v cc is stable until the specified operation can be ini tiated. these parameters are periodically sampled and not 100% tested. (2)typical values are for t a = 25c and v cc = 5.0v symbol parameter min. max. unit f scl scl clock frequency 0 1 mhz t aa(2) scl low to sda data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setup time (for a repeated start co ndition) 0.6 s t hd:dat data in hold time 10 ns t su:dat data in setup time 100 ns t r sda and scl rise time 20+0.1xc b (1) 300 ns t f sda and scl fall time 20+0.1xc b (1) 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 0 s t nol rst to scl non-overlap 500 ns t rdv rst low to sda valid during response to reset 0 450 ns t cdv clk low to sda valid during response to reset 0 450 ns t rst rst high time 1.5 s t su:rst rst setup time 500 ns symbol parameter min. typ. (2) max. unit t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms
x76f400 characteristics subject to change without notice. 10 of 15 rev 1.0 7/5/00 www.icmic.com nonvolatile write cycle timing note: (1)t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed i nternal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatil e write by the user, unless acknowledge polling is used. bus timing write cycle timing rst timing diagram ? response to a synchronous reset symbol parameter min. typ . (1) max. unit t wc (1) write cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda t wc 8 th bit of last byte ack stop condition start condition t rst t nol t high_rst t low_rst t cdv t rdv t su:rst data bit (1) data bit (2) 1 st clk pulse 2 nd clk pulse 3 rd clk pulse i/o clk rst t nol
x76f400 characteristics subject to change without notice. 11 of 15 rev 1.0 7/5/00 www.icmic.com guidelines for calculating typical values of bus pu ll up resistors 100 80 60 40 20 bus capacitance in pf r min r max 20 40 60 80 100 r min v ccmax i olmin -------------------------- 1.8 k = = r max t r c bus ------------------ = t r = maximum allowable sda rise time pull up resistance in k
x76f400 characteristics subject to change without notice. 12 of 15 rev 1.0 7/5/00 www.icmic.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8 - lead plastic smal l outline gull wing package type s note: all dimensions in inches (in parentheses in m illimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x76f400 characteristics subject to change without notice. 13 of 15 rev 1.0 7/5/00 www.icmic.com packaging information note: all dimensions in inches (in parentheses in m illimeters) 8 - lead plastic, tssop, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ? 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
x76f400 rev 1.0 7/5/00 www.icmic.com characteristics subject to change without notice. 14 of 15 packaging information 3.369 0.002 (85.57 0.05) 2.125 0.002 (53.98 0.05) 0.593 0.002 (15.06 0.05) 3 max. draft angle (all around) notes: 1. all dimensions are in inches and (millimeters). 2. material: white pvc molded plastic with anti-sta tic additive. 3. surface finish suitable for offset printing. 0.430 0.002 (10.92 0.05) 0.475 0.010 (12.07 0.25) 0.478 0.002 (12.14 0.05) r. 0.125 (3.18) (4x) 0.31 0.0005 (.079 0.0127) scale: 5x aa r. 0.030 (0.76) (4x) mold gate detail section a-a smart card type y 3003 ill 02.1
x76f400 characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and pa tent indemnification provisions appearing in its term s of sale only. xicor, inc. makes no warranty, express, statu tory, implied, or by description regardin g the information set forth herein or regarding the freedom of the described devices from patent infringem ent. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. re serves the right to discontinue production and change spec ifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any cir cuitry other than circuitry embodied in a xicor, inc. p roduct. no other circuits, patents, or licenses are implie d. trademark disclaimer: xicor and the xicor logo are registered trademarks of xi cor, inc. autostore, direct write, block lock, serialflash , mps, and xdcp are also trademarks of xicor, inc. all o thers belong to their respective owners. u.s. patents xicor products are covered by one or more of the followin g u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,4 50,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,8 74,967; 4,883,976; 4,980,859; 5,012,132; 5,003, 197; 5,02 3,694; 5,084,667; 5,153,880; 5,153,691; 5,161,13 7; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,5 73; 5,835,409; 5,977,585. foreign patents and additi onal patents pending. life related policy in situations where semiconductor component failure may e ndanger life, system designers using this product should des ign the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor?s products are not authorized for use in critical c omponents in life support devices or systems. 1.life support devices or systems are devices or systems which, (a ) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructio ns for use provided in the labeling, can be reasonably e xpected to result in a significant injury to the user. 2.a critical component is any component of a life suppor t device or system whose failure to perform can be reasona bly expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?xicor, inc. 2000 patents pending rev 1.0 7/5/00 www.icmic.com ordering information part mark convention v cc limits blank = 5v 10% 2.5 = 2.5v to 5.5v te mperature range blank = commercial = 0c to +70c i = industrial= ?40c to +85c package s8 = 8-lead soic v8 = 8 -lead tssop h = die in waffle packs (contact factory) w = die in wafer form (contact factory) y = smartcard device x76f400 p t g ? v 8 - lead tssop yww 8 - lead soic x76f400 x g xx blank = 8-lead soic g = rohs compliant lead free ae = 2.5 to 5.5v, 0 to +70c af = 2.5 to 5.5v, -40 to +85c blank = 4.5 to 5.5v, 0 to +70c i = 4.5 to 5.5v, -40 to +85c blank = 4.5 to 5.5v, 0 to 70c i = 4.5 to 5.5v, -40 to +85c ae = 2.5 to 5.5v, 0 to 70c af = 2.5 to 5.5v, -40 to +85c 7640xx rohs compliant lead free package blank ? standard package. non lead free

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